The present invention relates to a signal delay apparatus, and more particularly, to a signal delay apparatus capable of obtaining delay signals which are highly accurate.
Heretofore, when causing a certain signal to have a given delay time, it has been common to use a delay line available on the market. A type of the internal structure of such a delay line includes a distribution constant type having a structure like those of a coaxial cable and a delay cable, and a concentration constant type composed of discrete L and C, which make it possible to obtain accurate delay signals.
However, an analog delay line of this kind has a disadvantage in that it is extremely expensive.
On the other hand, as a method to obtain delay signals inexpensively, it can be considered to obtain desired delay time by linking plural delay elements each being an integral circuit composed of a digital circuit. In this method, however, it is impossible to obtain delay signals satisfying the necessary accuracy requirements, because the method has a disadvantage in that delay time is greatly influenced by dispersion in manufacturing steps and by variation of temperature, humidity and power voltage.
In order to enhance accuracy, therefore, there sometimes is used a mixture type delay line wherein an analog delay line is employed outside a digital circuit as a chip to be attached outside. However, even in this case, it has been impossible to avoid cost increase due to the matters of expenses for development and a unit price.
With regard to a delay line of a digital type, the inventors of the invention have proposed in TOKKAIHEI 5-275788 an apparatus wherein a delay signal specifically related to an input signal is detected by a standard signal detecting means from plural delay signals outputted from a signal delay means, and wherein a delay signal to be outputted by an output signal determining means based on the results of detection made by the standard signal detecting means is selectively outputted.
Though it is possible, due to this delay line, to accurately find out, from plural delay signals, the delay signal having desired delay time, the number of steps each representing an output signal determining means (selector) which finally selects the desired delay signal is increased as the desired accuracy is enhanced, making it impossible to ignore the delay generated in the selector.
For example, even when a delay signal having the desired delay time is found out at the accuracy of 1 nS from a signal delay means wherein 400 delay element steps are linked in series, a selector of 400 inputs takes 9 steps (400, 200, 100, 50, 25, 12, 6, 3. 1). Therefore, when one step of the selector includes a delay of 1 nS, the final delay of 9 nS is supposed to be generated. When it is impossible to design all path-lengths each covering from a delay element at each step to a selector at the final step to be the same, an error caused by a difference of the path-length is supposed to be generated.
Even if the desired delay signal is found out accurately, the final accuracy is lowered by a delay or an error generated in the course of selecting and outputting, which has been a problem.
Recently, in particular, image forming apparatus is required to output images at high speed, and the accuracy desired is getting higher and higher year after year. Accordingly, the number of inputs to a selector is considered to be increased, giving a hint of a possibility that a delay or an error at the selector is increased. Therefore, it is extremely difficult to finally obtain delay signals accurately.